library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt24_hour is
	port(clk_hour:in std_logic;--clock signal(carry signal from cnt60_min.vhd)
		set_hour:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_hour:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_hour:out std_logic_vector(7 downto 0)-- output 8421 code
		);
end cnt24_hour;

architecture func of cnt24_hour is
	signal temp1:std_logic_vector(3 downto 0);--right digit for hour signal
	signal temp10:std_logic_vector(3 downto 0);--left digit for hour signal
begin
		process(set_hour,clk_hour,clr)
		begin
			if(clr='0') then 
				temp1<="0000";
				temp10<="0000";
			elsif(set_hour='1') then
				temp10<=qin_hour(7 downto 4);
				temp1<=qin_hour(3 downto 0);
			elsif(clk_hour'event and clk_hour='1') then
				if(temp10=2 and temp1=3) then
					temp1<="0000";
					temp10<="0000";
				elsif(temp1=9) then 
					temp1<="0000";
					temp10<=temp10+1;
				else
					temp1<=temp1+1;
			end if;
			qout_hour<=temp10 & temp1;
		end process;
end func;